The diode current waveform shown, along with the description of the voltage waveform in the problem, indicate that the diode current goes negative before the voltage across the diode is affected. How is this possible? Because L and C are large, the fet voltage would start to decrease at the same time the diode voltage starts to increase. Why does the voltage across the fet remain constant until after time interval ta? I would think that the voltage across the fet would start to rise as soon as it starts to conduct current.
If there is a constant 5A through the inductor, it would go directly to the load when the diode is conducting. With a 400V output, 5A * 400V = 2,000 watts. (The problem says 500W.)
Is part b asking what are the switching losses in M, the switching losses in D, and the two added together?
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The inductor current only goes through the diode when the device is on. The average value of the output current over one switching period is 1/4 of the inductor current, or 1.25 A, which is how we have 500 W.
Part b is indeed asking for losses in each device and the sum.
I confess that I don't fully understand the dynamics of the FET voltage waveform, but I know you can get voltage spikes in any switched inductive circuit and the FET voltage doesn't necessarily start dropping immediately, which is why it heats up and dissipates power. This one probably would have a heatsink on it the size of my iPod, and a fan too. Even if it is dissipating 25 watts or so, that only has about a 5% impact on the efficiency of the converter.
The diode is still forward biased during the ta interval, even though there is reverse current, which is why the FET voltage remains high. At the end of ta, the diode turns off and the FET voltage drops.
While the diode is conducting, the 5A must charge the capacitor and go to the load. When the diode is off, doesn't the capacitor source current to the load? Are we acknowledging that there are ripple voltages and currents (even though we are neglecting them)?
How can there be negative current through the diode that doesn't affect the voltage across the fet? If the current is continuous through the inductor, wouldn't the negative current through the diode cause the voltage across the fet to decrease? Current would be coming from the inductor and the diode and therefore must flow through the fet.
The recovery current in the diode comes off of the capacitor. The constant 5A through the inductor gets split between the FET and the diode in interval ta, and gets added to the recovery current through the FET in tb. When the diode is on and the FET is off, the inductor current charges the capacitor as well as going to the load. The capacitor is there to help keep the load current steady.
The voltage vds seemingly can't drop while the diode is forward biased, which could be part of the reason we're interested in mitigating this reverse recovery problem - to eliminate this egregious waste of energy spent heating up the transistor at 400 volts.
I guess one way to think about it is that when the gate voltage on the FET goes up, it starts opening the channel and dumping charges, and once those charges are dumped it can drop the voltage. But the diode has charges to dump too before its reverse voltage can go up, and those charges get sent through the FET. While those charges remain in the diode, the FET is trying to dump them but has to work really hard - for every Coulomb it dumps it has to dissipate 400 Joules. At 80 nC each period, that works out to 32 microjoules. Multiply that by 200 kHz and it's dissipating 6.4 mW just to get rid of the Qr.
I get quite a bit more than 6.4 mW in losses, but I suppose it's not all coming from Qr.
Anyway, I hope I'm being helpful (I also hope I'm right).
Sorry, make that 6.4 watts, not milliwatts. I still get higher losses than that.
And another correction: In ta, all of the inductor current is going through the FET. It is in the 10 ns before ta that it gets split.
Confused yet?
The way I look at it, when the diode is going through reverse recovery, it means that electrons have to be injected into the forward biased junction so conventional current is flowing out of the anode(id) so by KCL im=iL+id, this additional id causes the current spike in the transistor.
10ns before ta the current in M is rising at the same rate as current in D is falling. At ta when id=0, im=5A, after ta untill the start of tb, diode goes through rr and is dumping its charges into M so current in M continues to rise beyond 5A. Also during ta thro' tb, diode is still ON as its rr has not finished and M is OFF. At tb most of the charge from the diode has been removed, the jn has depleted and it is OFF. So id rises to 0 and consequently im settles at 5A. Also it is during tb that Vds starts to drop from 400V to 0V and Vd rises from 0V to 400V.
Isn't M ON during the rr of the diode? Otherwise how would there be any switching loss in the transistor?
wrich,
You ask a good question. I have being puzzling over the M voltage waveform for quite a while. The only thing that makes sense to me is the way I explained in my remarks above. However that does not explin how M is OFF during ta but drain current is still rising and infact peaking. The only explanation I gave myself is because we are considering ideal devices here and in reality maybe M is slightly turned ON.
I looked at an application note AN603 from STMicro and that verifies my explanation above. Now I only hope the math I did is correct.
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