In this problem, I think that on the turn off of Q2 the voltage vs goes up from 0 to V_bus and then overshoots and starts ringing. At this point (t_c) we have Q1 and D1 both on. This creates a parallel LC circuit, and when I try to solve Ldi/dt = V_bus = w_0 L dj/dtheta V_bus/R_0 I get that dj/dtheta = 1 which doesn't make sense to me for the circle. Am I misunderstanding the behavior of the circuit at this time?
Also, for the initial condition, can we assume that this is a small enough amount of time that i_L stay steady at -I_L0 for the entire time it is charging the capacitors to get v_s up to V_bus?
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I'm not sure, but I don't think this problem is about looking at any ringing after vs=Vbus. We're interested in the state plane diagram that gets us there.
I have Ldi/dt=vs and 2Cdvs/dt=-iL. This gives me diL/dtheta=m and dms/dtheta=-j, which puts my center at the origin and the curve going CCW in the 4th quadrant, with radius A=J. We want J to be at least 1 if we're going to get to vs=Vbus.
Somebody please tell me if I've been out in the sun too long...
Annotated L2 slides, page 17: immediately after M2 turns off at t=0, no device is conducting, voltage goes up from 0V. The same thing happens in HW6 pb2: after Q2 is turned off, no devices are conducting, vs goes up from 0V and iL goes up from –Ilo.
Equivalent circuit is just L and Ceqv=2*C without any DC sources, since no devices is conducting. Exclusion of DC sources means that steady state values for both vs and iL are zero; center of the circle is at (0,0).
Good, that agrees with what I have, but it's a more intuitive way of getting it. I'm going to have to make a habit of looking at the older lecture slides...
I understand what you are saying about no devices being on between t0 and tc. I was incorrectly thinking that D1 was conducting during this time.
I am still very confused about when the ringing will occur and what the current is doing. I thought the ringing would occur when v_s gets to Vbus. At this point wouldn't D1 turn on and change the resonant circuit? Also, wouldn't this make the steady state value of v_S during the time period of interest Vbus? And where do you derive that the steady state value of I_L is 0?
Steady state values in HW6 pb2 are derived by comparing the HW6 pb2 equivalent circuit to the reference circuit:
Looking at the reference HW1 circuit from L17 annotated slides, page 1: steady state value of v(t) is V and steady state of i(t) is I: steady state values of the v(t) and i(t) in the reference circuit are equal to the values of corresponding DC sources.
HW6 pb2 0<t<tc: equivalent circuit is just L and Ceqv=2*C, without any DC sources, which means that steady state values for vs and iL are both zero.
correction: L17 page2
In general, ringing occurs when the equivalent circuit contains the resonant tank: both L and C. In HW6 pb2: after Q2 is turned off, the equivalent circuit contains both L and Ceqv=2*C, which means that it will ring. Ringing is represented by a circle in the state plane.
If vs can reach Vbus: the circuit will ring from t=0 up to t=tc(when the Vbus is reached), which is a quarter of the sine wave maximum. The current iL rings too(follows the circle) from iL(t=o)=-IL0 up to some value iL(t=tc)≤0. At time t=tc: vs=Vbus, D1 turns on and changes the equivalent circuit by replacing Ceqv with Vbus. The circuit now does not ring(circuit contains L only): vs=Vbus and iL ramps up as a linear function in time. This is a represented by a straight line in the state plane.
If vs cannot reach Vbus: the circuit rings(follows the circle) but D1 will not turn on and ZVS of Q1 is not obtained.
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