From class I got the impression that all converters of the same type follow the same state
plane analysis. I get a little confused when I compare the ZVS-QSW buck converter from class with the ZVS-QSW flyback in this problem. It looks to me like the behavior of the D_2 diode from the class example differs from that of the diode on the secondary of the flyback. In
the buck, when D_2 is conducting, it creates a short across the resonant capacitor so there is no voltage difference across the capacitor. In the flyback when the diode on the secondary is conducting and the transistors on the primary are not, then it seems you would still get a resonant circuit which completely changes the state plane diagram. Am I missing something here?
2 comments:
Hi Audrey,
You are right when you say that the state plane can be different depending on where you place the capacitance. Clearly when diode D2 is conducting the voltage across the capacitance is Vg+V/n. Conversely, when the D1 diode conducts, the voltage across that cap is zero. This would seem to give you some weird inverse of the buck case.
However, if you work out the state plane I bet you'll find that it will look very similar, just with some sort of offset. In an truly prolific waste of time, I did this with the last homework. (Actually, it's worthwhile to do once.)
With these switch networks, the V1,V2,I1,I2 values will be the same regardless of where that cap is as long as you are consistent. However, the stress on the individual capacitances will have some sort of offset if they are not in DC parallel with V2. If you keep a strict interpretation of the schematic, you will get a different state plane, but the same terminal results.
If you want the same state plane as the buck here is a simple approach that I took:
Push through the transformer to the primary side to give yourself a buck-boost configuration (The diode and output voltage change direction, move the fet to the top). I always find it easier to look at the "grandparent" converter.
Now simply move one end of that cap from Vg and stick it over onto the -V/n node so the capacitor is in parallel with the diode. -V/n and Vg are DC values so we are safe doing that. There is the configuration we are used to seeing and the state plane will look the same.
--Aaron
Thanks for the explanation Aaron. I was confused because I thought we would still have a resonant circuit during the output diode on-state, but as you point out in your last paragraph, the capacitor voltage is purely DC during this state so there will not be resonance.
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